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| Advanced Communication Devices Data Sheet: ACD80800 Address Resolution Logic (8K MAC Addresses) ACD Confidential. Do Not Reproduce. Use under Non-Disclosure Agreement only. Rev.1.0.0.E Last Update: September 19, 2000 Please check ACD's website for update information before starting a design Web site: http://www.acdcorp.com/tech.html or Contact ACD at: Email: support@acdcorp.com Tel: 510-354-6810 Fax: 510-354-6834 ACD Confidential Material For ACD authorized customer use only. No reproduction or redistribution without ACD's prior permission. 1 Data Sheet: ACD80800 CONTENT LIST 1. SUMMARY 2. FEATURES 3. FUNCTIONAL DESCRIPTION 4. PIN DESCRIPTION 5. INTERFACE DESCRIPTION 6. REGISTER DESCRIPTION 7. COMMAND DESCRIPTION 8. TIMING DESCRIPTION 9. ELECTRICAL SPECIFICATION ACD Confidential. Do Not Reproduce. Use under Non-Disclosure Agreement only. 10. PACKAGING 2 Data Sheet: ACD80800 The ACD80800 serves as an Address Resolution Logic for ACD's switch controller chips (ACD82124, ACD82012 etc.) through a glueless ARL interface. It automatically builds up an address table and can map up to 8K MAC addresses into their associated ports. The ACD80800 can work without a CPU in a unmanaged switch system, or with a CPU and an ACD MIB (ACD80900 Management Information Base). A direct input/output interface is integrated to support a management CPU. The CPU can configure the operation mode of the ACD80800, learn all the addresses in the address table, add new addresses into the table, control security or filtering features of each address entry, etc. The ACD80800 is designed with such a high performance that, it will never slow down the frame switching operation conducted by the ACD's switch controllers. Together with the non-blocking architecture of the ACD's switch controllers, the chip set (a ACD switch controller plus the ACD80800, plus ACD80900 in a managed switch system) can provide wire speed forwarding rate under any type of traffic load. * * * * * * * * * * * * * * * Supports up to 8K MAC address lookup Provides Glueless ARL Interface with ACD's switch controller chip Provides Direct Input/Output type of interface for the management CPU Provides UART type of interface for the management CPU Wire speed address lookup time. Wire speed address learning time. Address can be automatically learned from switch without THE CPU intervention Address can be manually added by the CPU through the CPU interface Each MAC address can be secured by the CPU from being changed or aged out Each MAC address can be marked by the CPU from receiving any frame Each newly learned MAC address is notified to the CPU Each aged out MAC address is notified to the CPU Automatic address aging control, with configurable aging period 0.35 micron, 3.3V CMOS technology 128-Pin PQFP package Figure-1: ACD80800 Used in A Managed n-Port Fast Ethernet Switch System ACD Confidential. Do Not Reproduce. Use under Non-Disclosure Agreement only. P(n-1) P(n-2) P(n-3) ACD82xxx n-Port Fast Ethernet Switch Controller P1 P0 ACD80900 MIB CPU ACD80800 Address Resolution Logic ASRAM 3 Data Sheet: ACD80800 1. SUMMARY 2. FEATURES ACD80800 provides Address Resolution service for ACD's switch controller chip. ACD80800 provides a glueless interface with ACD's switch controller, and is used to build an address table and provide address lookup service to ACD's switch controller. Figure 2 is a block diagram of ACD80800. Traffic Snooping All Ethernet frames received by ACD's switch controller have to be stored into memory buffer. As the frame data are written into memory, the status of the data shown on the data bus are displayed by ACD's switch controller through a state bus. ACD80800's Switch Controller Interface contains the signals of the data bus and the state bus. By snooping the data bus and the state bus of ACD's switch controller, ACD80800 can detect the occurrence of any destination MAC address and source MAC address embedded inside each frame. Address Learning Each source address caught from the data bus, together with the ID of the ingress port, is passed to the Address Learning Engine of ACD80800. The Address Address Aging After each source address is learned into the address table, it has to be refreshed at least once within each address aging period. Refresh means it is caught again from the switch interface. If it has not occurred for a pre-set aging period, the address aging engine will remove the address from the address table. After an address is removed by the address aging engine, the CPU will be notified through interrupt request that it needs to read this aged out address so that it can remove this address from the CPU's address table. Address Lookup Each destination address is passed to the Address Figure-2. ACD80800 Block Diagram ACD Confidential. Do Not Reproduce. Use under Non-Disclosure Agreement only. Switch Interface CPU Interface Command Registers Address Registers Address Learning Engine Address Aging Engine Address Lookup Engine CPU Interface Engine Address Table (8K Entries) Data Registers Control Registers 4 Data Sheet: ACD80800 3. FUNCTIONAL DESCRIPTION Learning Engine will first determine whether the frame is a valid frame. For a valid frame, it will first try to find the source address from the current address table. If that address doesn't exist, or if it does exist but the port ID associated with the MAC address is not the ingress port, the address will be learned into the address table. After an address is learned by the address learning engine, the CPU will be notified to read this newly learned address so that it can add it into the CPU's address table. CPU Interface ACD80800 provides a direct input/output type of interface for a management CPU to access various kind of registers inside ACD80800. The interface has 8-bit data bus, and 5-bit address bus. The timing of read and write operation is controlled by output enable signal and write enable signal. For details of CPU interface timing information, refer to the section of "Timing Description." The CPU can also choose to access the registers of ACD80800 by sending commands to the UART data input line. Each command is consisted by action (read or write), register type, register index, and data. Each result of command execution is returned to the CPU through the UART data output line. CPU Interface Registers ACD80800 provides a bunch of registers for the control CPU Interface Engine The command sent by the control CPU is executed by the CPU Interface Engine. For example, the CPU may send a command to learn the first newly-learned address. The CPU Interface Engine is responsible to find the newly-learned address from the address table, and passes it to CPU. The CPU may request to learn next newly-learned address. Then, it is again the responsibility of the CPU Interface Engine to search for next newly-learned address from the address table. Address Table The address table can hold up to 8K MAC addresses, together with the associated port ID, security flag, filtering flag, new flag, aging information etc. The address table resides in the embedded SRAM inside ACD80800. 5 ACD Confidential. Do Not Reproduce. Use under Non-Disclosure Agreement only. Data Sheet: ACD80800 Lookup Engine of ACD80800. The Address Lookup Engine checks if the destination address matches with any existing address in the address table. If it does, ACD80800 returns the associated Port ID to ACD's switch controller through the output data bus. Otherwise, a no match result is passed to ACD's switch controller through the output data bus. CPU. Through the registers, the CPU can read all address entries of the address table, delete particular addresses from the table, add particular addresses into the table, secure an address from being changed, set filtering on some addresses, change the hashing algorithm etc. Through a proper interrupt request signal, the CPU can be notified whenever it needs to retrieve data for a newly-learned address or an aged-out address so that the CPU can build an exact same address table learned by ACD80800. Figure-3: Pin Diagram Of ACD80800 (The ARL Chip) 128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 108 SWDI39 SWDI38 SWDI37 SWDI36 SWDI35 SWDI34 SWDI33 SWDI32 SWDI31 SWDI30 VDD VDD SWDO0 SWDO1 SWDO2 SWDO3 SWDOV GND VDD SWDI0 SWDI1 SWDI2 SWDI3 SWDI4 SWDI5 GND 6 ACD Confidential. Do Not Reproduce. Use under Non-Disclosure Agreement only. GND SWDI63 SWDI62 SWDI61 SWDI60 SWDI59 SWDI58 SWDI57 SWDI56 SWDI55 SWDI54 SWDI53 SWDI52 SWDI51 SWDI50 SWDI49 SWDI48 VDD GND SWDI47 SWDI46 SWDI45 SWDI44 SWDI43 SWDI42 SWDI41 SWDI40 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 107 106 105 104 103 VDD GND nCPUCS nCPUWE nCPUOE CPUA4 CPUA3 CPUA2 CPUA1 CPUA0 GND VDD CPUD7 CPUD6 CPUD5 CPUD4 CPUD3 CPUD2 CPUD1 CPUD0 CPUIRQ GND VDD UARTDO UARTDI GND 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 VDD GND WCHDOG nRESET NC SWDIR1 SWDIR0 SWSTAT3 SWSTAT2 SWSTAT1 SWSTAT0 GND VDD SWEOF SWSYNC SWPID4 SWPID3 SWPID2 SWPID1 SWPID0 SWCLK GND GND GND SWDI29 SWDI28 SWDI27 SWDI26 SWDI25 SWDI24 SWDI23 SWDI22 SWDI21 SWDI20 SWDI19 SWDI18 SWDI17 SWDI16 SWDI15 SWDI14 SWDI13 SWDI12 SWDI11 SWDI10 SWDI9 SWDI8 SWDI7 SWDI6 VDD Data Sheet: ACD80800 4. PIN DESCRIPTIONS Pin Table Pin Name 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 GND S WDI63 S WDI62 S WDI61 S WDI60 S WDI59 S WDI58 S WDI57 S WDI56 S WDI55 S WDI54 S WDI53 S WDI52 S WDI51 S WDI50 S WDI49 S WDI48 VDD GND S WDI47 S WDI46 S WDI45 S WDI44 S WDI43 S WDI42 S WDI41 S WDI40 S WDI39 S WDI38 S WDI37 S WDI36 S WDI35 S WDI34 S WDI33 S WDI32 S WDI31 S WDI30 VDD GND S WDI29 S WDI28 S WDI27 S WDI26 S WDI25 S WDI24 S WDI23 S WDI22 S WDI21 S WDI20 S WDI19 S WDI18 S WDI17 S WDI16 S WDI15 S WDI14 S WDI13 S WDI12 S WDI11 S WDI10 S WDI9 S WDI8 S WDI7 S WDI6 VDD Description Ground. Data from s witch controller chip. Data from s witch controller chip. Data from s witch controller chip. Data from s witch controller chip. Data from s witch controller chip. Data from s witch controller chip. Data from s witch controller chip. Data from s witch controller chip. Data from s witch controller chip. Data from s witch controller chip. Data from s witch controller chip. Data from s witch controller chip. Data from s witch controller chip. Data from s witch controller chip. Data from s witch controller chip. Data from s witch controller chip. 3.3V power s upply. Ground. Data from s witch controller chip. Data from s witch controller chip. Data from s witch controller chip. Data from s witch controller chip. Data from s witch controller chip. Data from s witch controller chip. Data from s witch controller chip. Data from s witch controller chip. Data from s witch controller chip. Data from s witch controller chip. Data from s witch controller chip. Data from s witch controller chip. Data from s witch controller chip. Data from s witch controller chip. Data from s witch controller chip. Data from s witch controller chip. Data from s witch controller chip. Data from s witch controller chip. 3.3V power s upply. Ground. Data from s witch controller chip. Data from s witch controller chip. Data from s witch controller chip. Data from s witch controller chip. Data from s witch controller chip. Data from s witch controller chip. Data from s witch controller chip. Data from s witch controller chip. Data from s witch controller chip. Data from s witch controller chip. Data from s witch controller chip. Data from s witch controller chip. Data from s witch controller chip. Data from s witch controller chip. Data from s witch controller chip. Data from s witch controller chip. Data from s witch controller chip. Data from s witch controller chip. Data from s witch controller chip. Data from s witch controller chip. Data from s witch controller chip. Data from s witch controller chip. Data from s witch controller chip. Data from s witch controller chip. 3.3V power s upply. I/O 3.3V 3.3V 3.3V 3.3V 3.3V 3.3V 3.3V 3.3V 3.3V 3.3V 3.3V 3.3V 3.3V 3.3V 3.3V 3.3V I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I - Pin Name 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 GND S WDI5 S WDI4 S WDI3 S WDI2 S WDI1 S WDI0 VDD GND S WDOV S WDO3 S WDO2 S WDO1 S WDO0 VDD GND GND S WCL K S WPID0 S WPID1 S WPID2 S WPID3 S WPID4 S WS YNC S WE OF VDD GND S WS T AT 0 S WS T AT 1 S WS T AT 2 S WS T AT 3 S WDIR0 S WDIR1 NC nRE S E T WCHDOG GND VDD GND UART DI UART DO VDD GND CPUIRQ CPUD0 CPUD1 CPUD2 CPUD3 CPUD4 CPUD5 CPUD6 CPUD7 VDD GND CPUA0 CPUA1 CPUA2 CPUA3 CPUA4 nCPUOE nCPUWE nCPUCS GND VDD Description Ground. Data from s witch controller chip. Data from s witch controller chip. Data from s witch controller chip. Data from s witch controller chip. Data from s witch controller chip. Data from s witch controller chip. 3.3V power s upply. Ground. Output data valid s ignal to s witch controller chip. Output data to s witch controller chip. Output data to s witch controller chip. Output data to s witch controller chip. Output data to s witch controller chip. 3.3V power s upply. Ground. Ground. 50MHz reference clock s ignal from s witch controller chip. Port ID indication s ignal from s witch controller chip. Port ID indication s ignal from s witch controller chip. Port ID indication s ignal from s witch controller chip. Port ID indication s ignal from s witch controller chip. Port ID indication s ignal from s witch controller chip. Port 0 indication s ignal from s witch controller chip. E nd Of F rame indication s ignal from s witch controller chip. 3.3V power s upply. Ground. Data S tatus s ignal from s witch controller chip. Data S tatus s ignal from s witch controller chip. Data S tatus s ignal from s witch controller chip. Data S tatus s ignal from s witch controller chip. Data direction indication s ignal from s witch controller chip. Data direction indication s ignal from s witch controller chip. Not connected. Hardware res et pin. Watch dog s ignal. Ground. 3.3V power s upply. Ground. UART data input line. UART data output line. 3.3V power s upply. Ground. Interrupt reques t. CPU data bus . CPU data bus . CPU data bus . CPU data bus . CPU data bus . CPU data bus . CPU data bus . CPU data bus . 3.3V power s upply. Ground. CPU addres s bus . CPU addres s bus . CPU addres s bus . CPU addres s bus . CPU addres s bus . Output E nable s ignal from CPU. Write E nable s ignal from CPU. Chip S elect s ignal from CPU. Ground. 3.3V power s upply. I/O 3.3V 3.3V 3.3V 3.3V 3.3V 3.3V I I I I I I O O O O O I I I I I I I I I I I I I I I O I O O I/ O I/ O I/ O I/ O I/ O I/ O I/ O I/ O I I I I I I I I - 3.3V 3.3V 3.3V 3.3V 3.3V 3.3V 3.3V 3.3V 3.3V 3.3V 3.3V 3.3V 3.3V 3.3V 3.3V 3.3V 3.3V 3.3V 3.3V 3.3V 3.3V 3.3V 3.3V 3.3V 3.3V 3.3V 3.3V 3.3V 3.3V 3.3V 3.3V 3.3V 3.3V 3.3V 3.3V 3.3V 3.3V 3.3V 3.3V 3.3V 3.3V 3.3V 3.3V 3.3V 3.3V 3.3V 3.3V 3.3V 3.3V 7 ACD Confidential. Do Not Reproduce. Use under Non-Disclosure Agreement only. 3.3V 3.3V 3.3V 3.3V 3.3V 3.3V 3.3V 3.3V 3.3V 3.3V 3.3V 3.3V 3.3V 3.3V 3.3V 3.3V 3.3V 3.3V 3.3V 3.3V 3.3V 3.3V 3.3V 3.3V 3.3V 3.3V 3.3V 3.3V 3.3V 3.3V 3.3V 3.3V 3.3V 3.3V Data Sheet: ACD80800 Switch Interface Switch interface provides a communication channel between ACD's switch controller chip and ACD80800. As a frame is being received by ACD's switch controller chip , the destination address and source address of the frame are snooped from the SWDIx lines of ACD80800, with respect to the SWCLK signal. ACD80800 carries a lookup process for each destination address, and a learning process for each source address. The result of the lookup is returned to the switch controller chip through the SWDOx lines. Table 1 shows the associated signals in the Switch Interface. Table-1: Switch Interface Name SWDI0 ~ SWDI63 SWSTAT0 ~ SWSTAT3 SWEOF SWDIR0 ~ SWDIR1 SWSYNC SWPID0 ~ SWPID4 SWCLK SWDOV SWDO0 ~ SWDO3 Type I I I I I I I O O Description Input data, which can be 48bit or 64-bit wide Input data state End of frame indication signal Data direction indication signal Port synchronization signal Port-ID indication signal Reference clock Output data valid signal Output data which can be 2bit or 4-bit wide * Note: error type depends on SWDIR is 01 or 10. SWSYNC is used to indicate port 0 is driving the Data bus. It is used when the bus is evenly allocated in a time division multiplexing manner, such that a monitoring device can implement a counter to indicate the ID of the port which is driving the SWDI bus, and use SWSYNC signal to reset the counter. When SWSYNC is in use, SWPID is ignored. SWPID is used to indicate the ID of the port which is driving the Data bus. When SWPID is in use, SWSYNC is ignored. SWEOF is used to indicate the start and end of a frame. It is always asserted when the corresponding port is idling. The start of a frame is indicated by a high-to-low transition of SWEOF signal. The end of a frame is indicated by a low to high transition of SWEOF signal. SWCLK is used to provide timing reference of input data snooping and output data latching. The signal is also used as the system clock of the chip. SWDOV is used to indicate the start of a lookup result package. SWDOx is used to return the result of lookup to ACD's switch controller chip. Data is latched onto SWDOx bus with respect to the rising edge of SWCLK signal. Each result package is consisted by 5-bit source port ID, 2bit result, and 5-bit destination port ID. The 2-bit result field is defined as 01 for match, with the port ID shown by the 5-bit destination port ID field; 10 for no match; 11 for forced disregard (filtering). ACD Confidential. Do Not Reproduce. Use under Non-Disclosure Agreement only. The SWDIx signal comes from the SRAM Data bus of ACD's switch controller chip . Since all data of the received frames have to be written into the shared memory through the Data bus, the bus can be monitored for occurrence of DA and SA values, indicated by the associated state bits. The signals in SWDIx bus can be a 48-bit or 64-bit wide data bus. For a 48-bit wide bus, the first word will be the DA and the second word will be the SA. For a 64-bit wide bus, DA is the first 48-bit of first word, SA is the last 16-bit of first word plus first 32bit of second word. SWDIR is a 2-bit signal to indicate the direction of the data displayed on the SWDI bus, 01 for receiving, 10 for transmitting, 00 or 11 for other states. ACD80800 only deals with the received data. SWSTAT bus is a 4-bit signal, used to indicate the meaning (status) of the data. The 4-bit status is defined as: 8 Data Sheet: ACD80800 5. INTERFACE DESCRIPTION * * * * * * * * * * * * * * * * 0000 - Third to Last word 0001 - First word 0010 - Second word 0011 - Reserved 0100 - Reserved 0101 - Drop event 0110 - Jabber 0111 - False carrier 1000 - Alignment error 1001 - Flow control/collision* 1010 - Short event/excessive collision* 1011 - Runt/Late collision* 1100 - Symbol error 1101 - FCS error 1110 - Long event 1111 - Reserved * The CPU interface provides a communication channel between the CPU and the ACD80800. Basically, the CPU sends command to the ACD80800 by writing into associated registers, and retrieve result from ACD80800 by reading corresponding registers. The registers are described in the section of "Register Description." The CPU interface signals are described by table 2: * * * Table-2: CPU Interface Name CPUA0 ~ CPUA4 CPUD0 ~ CPUD7 nCPUOE nCPUWE nCPUCS CPUIRQ I/O I I/O I I I O Description 5 address lines for register selection. 8 data lines. Read enable signal, low active. Write enable signal, low active. Chip Select signal, low active. Interrupt request signal. Header is further defined as: b1:b0 - read or write, 01 for read, 11 for write b4:b2 - device number, 000 to 111 (0 to 7) b7:b5 - device type, 010 for ARL Address - 8-bit value used to select the register to access Data - 32-bit value, only the LSB is used for write operation, all 0 for read operation Checksum - 8-bit value of XOR of all bytes UARTDO is used to return the result of command execution to the CPU. The format of the result packet is shown as follows: Header Address Data Checksum UARTDI UARTDO I O UART input data line. UART output data line. where: * CPUAx is the address bus used to select the registers of the ACD80800. CPUDx is the data bus used to pass data between the CPU and the registers of the ACD80800. nCPUOE is used to control the timing of the read operation. nCPUWE is used to control the timing of the write operation. nCPUCS is used to make the ACD80800 active to the nCPUOE or nCPUWE signals. CPUIRQ is used to generate an interrupt request to the CPU. For each source of the interrupt, refer to the description of the interrupt source register. UARTDI is used by the control CPU to send command into the ACD80800. The baud rate will be automatically detected by the ACD80800. The result will be returned through the UARTDO line with the detected baud rate. The format of the command packet is shown as follows: * * * The ACD80800 will always check the CMD header to see if both the device type and the device number matches with its setting. If not, it ignores the command and will not generate any response to this command. Other Interface (table 3) Table-3: Other Interface Name I/O Description WCHDOG nRESET VDD O I Alive signal from ACD80800 to indicate it is working properly. Hardware reset signal, low active. 3.3V power supply. GND - Ground. Header Address Data Checksum WCHDOG signal is used to prevent the system from hitting dead-lock by any abnormal event. Under normal condition, the output signal from the WCHDOG pin will not stay at low for longer than 10ms. If the state of 9 ACD Confidential. Do Not Reproduce. Use under Non-Disclosure Agreement only. Header is further defined as: b1:b0 - read or write, 01 for read, 11 for write b4:b2 - device number, 000 to 111 (0 to 7) b7:b5 - device type, 010 for ARL Address - 8-bit value for address of the selected register Data - 32-bit value, only the LSB is used for read operation, all 0 for write operation Checksum - 8-bit value of XOR of all bytes Data Sheet: ACD80800 CPU Interface where: nRESET pin is used to do a hardware reset to the ACD80800. Please note that after a hardware reset, all learned address is cleared, and the address table has to be built again. Configuration Interface The following table shows the Power-On-Strobed configuration setting: The registers accessible to the CPU are described by table 4: Table-4: Register Description Reg. 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Name DataReg0 DataReg1 DataReg2 DataReg3 DataReg4 DataReg5 DataReg6 DataReg7 AddrReg0 AddrReg1 CmdReg RsltReg CfgReg IntSrcReg IntMskReg nLearnReg0 nLearnReg1 nLearnReg2 AgeTimeReg0 Description Byte 0 of data Byte 1 of data Byte 2 of data Byte 3 of data Byte 4 of data Byte 5 of data Byte 6 of data Byte 7 of data LSB of address value MSB of address value Command register Result register Configuration register Interrupt source register Interrupt mask register Address learning disable register for port 0 - 7 Address learning disable register for port 8 - 15 Address learning disable register for port 16 - 23 LSB of aging period register Power-On-Strobed Setting Name BIST Enable IC Test Enable DIO Enable Port ID Select NO CPU Description Boot-Internal-Self-Test for optional internal RAM test IC Manufacturer test use only: always pull low 1 = Data I/O 0 = UART Mode 1 = for 82124 or 82012 0 = reserved 11 = No CPU, 80800 will self initiate 00 = With CPU, 80800 will wait for CPU to initiate 75 Shared Pin# 78 77 76 74/111 110/109 16 17 18 114/113/112 01 = 48 bit ( 82124 or 82012) 10 = reserved 11 = 64 bit ( reserved ) 000 = ID for the only or the first UART ID 80800 on the system 001 = ID for the second 80800 on the system with two 80800s Note: High=1=Enable 19 20 21 AgeTimeReg 1 PosCfg0 PosCfg1 MSB of aging period register Power On Strobe configuration register 0 Power On Strobe configuration register 1 6. REGISTER DESCRIPTION ACD80800 provides a bunch of registers for the CPU to access the address table inside it. Command is sent to ACD80800 by writing into the associated registers. Before the CPU can pass a command to ACD80800, it must check the result register (register 11) to see if the command has been done. When the Result register indicates the command has been done, the CPU may need to retrieve the result of previous command first. After that, the CPU has to write the associated parameter of the command into the Data registers. Then, the CPU can write the command type The DataRegX are registers used to pass the parameter of the command to the ACD80800, and the result of the command to the CPU. The AddrRegX are registers used to specify the address associated with the command. The CmdReg is used to pass the type of command to the ACD80800. The command types are listed in table 5. The details of each command is described in the chapter of "Command Description." 10 ACD Confidential. Do Not Reproduce. Use under Non-Disclosure Agreement only. Bus Width 00 = 32 bit ( reserved ) Selection Data Sheet: ACD80800 WCHDOG remains at low state, the chip is not working properly and needs to be reset. into the command register. When a new command is written into the command register, ACD80800 will change the status of the Result register to 0. The Result register will indicate the completion of the command at the end of the execution. Before the completion of the execution, any command written into the command register is ignored by ACD80800. Command 0x09 0x0A 0x0B 0x0C 0x0D 0x10 0x11 0x20 0x21 0x30 0x31 0x40 0x41 0x50 0x51 0x60 0x61 0x80 0x81 Description Add the specified MAC address into the address table Set a lock for the specified MAC address Set a filtering flag for the specified MAC address Delete the specified MAC address from the address table Assign a port ID to the specified MAC address Read the first entry of the address table Read next entry of address book Read first valid entry Read next valid entry Read first new page Read next new page Read first aged page Read next aged page Read first locked page Read next locked page Read first filtered page Read next filtered page Read first page with specified PID Read next page with specified PID The IntMskReg is used to enable an interrupt source to generate an interrupt request. The bit definition is the same as IntSrcReg. A 1 in a bit enables the corresponding interrupt source to generate an interrupt request once it is set. The nLearnReg[2:0] are used to disable address learning activity from a particular port. If the bit corresponding to a port is set, ACD80800 will not try to learn new addresses from that port. The AgeTimeReg[1:0] are used to specify the period of address aging control. The aging period can be from 0 to 65535 units, with each unit counted as 2.684 second. The PosCfgReg0 is a configuration register whose default value is determined by the pull-up or pull-down status of the associated hardware pin. The bits of PosCfgReg0 is listed as follows: * * * * * bit 0 - BISTEN, shared with ARLDO0, 0 for no self test, 1 for enable self test bit 1 - TESTEN, shared with ARLDO1, 0 for normal operation, 1 for production test. bit 2 - DIOEN, shared with ARLDO2, 0 for using UART, 1 for using DIO. bit 3 - SYNCEN, shared with ARLDO3, 0 for using SWPID, 1 for using SWSYNC. bit 4 - NOCPU*, 0 for have a control CPU, 1 for do not have a control CPU. 0xFF System reset The RstReg is used to indicate the status of command execution. The result code is listed as follows: * * * 01 - command is being executed and is not done yet 10 - command is done with no error 1x - command is done, with error indicated by x, where x is a 4-bit error code: 0001 for cannot find the entry as specified The CfgReg is used to configure the way the ACD80800 works. The bit definition of CfgReg is described as: * * * * * bit 0 - disable address aging bit 1 - disable address lookup bit 2 - disable DA cache bit 3 - disable SA cache bit 7:4 - hashing algorithm selection, default is 0000 Note: When NOCPU is set as 0, ACD80800 will not start the initialization process until a System Start command is sent to the command register. The PosCfgReg1 is a configuration register whose default value is determined by the pull-up or pull-down status of the associated hardware pin. The bits of PosCfgReg1 is listed as follows: * * bit 1:0 - BUSMODE, shared with CPUD1:CPUD0, bus width selection, 01 for 48-bit, 10 for 64 bit. bit 2 - CPUGO, shared with CPUD2, only effective when NOCPU bit of PosCfgReg0 is set to 1. Setting CPUGO to 0 means The IntSrcReg is used to indicate what can cause interrupt request to CPU. The source of interrupt is listed as: 11 ACD Confidential. Do Not Reproduce. Use under Non-Disclosure Agreement only. Data Sheet: ACD80800 Table-5: Command List * * * * * * * * bit 0 - aged address exists bit 1 - new address exists bit 2 - reserved bit 3 - reserved bit 4 - bucket overflowed bit 5 - command is done bit 6 - system initialization is completed bit 7 - self test failure * Result: the MAC address will be removed from the address table. The result is indicated by the Result register. Command 0DH 7. COMMAND DESCRIPTION Command 09H Description: Assign the associated port number to the specified MAC address. Parameter: Store the MAC address into DataReg5 DataReg0, with DataReg5 contains the MSB of the MAC address and DataReg0 contains the LSB. Store the port number into DataReg6. Result: the port ID field of the entry containing the specified MAC address will be changed accordingly. The result is indicated by the Result register. Command 10H Description: Add the specified MAC address into the address table. Parameter: Store the MAC address into DataReg5 DataReg0, with DataReg5 contains the MSB of the MAC address and DataReg0 contains the LSB. Store the associated port number into DataReg6. Result: the MAC address will be stored into the address table if there is space available. The result is indicated by the Result register. Command 0AH Description: Read the first entry of the address table. Parameter: None Result: The result is indicated by the Result register. If the command is completed with no error, the content of the first entry of the address book will be stored into the Data registers. The MAC address will be stored into DataReg5 - DataReg0, with DataReg5 contains the MSB of the MAC address and DataReg0 contains the LSB. The port number is stored in DataReg6, and the Flag* bits are stored in DataReg7.The Read Pointer will be set to point to second entry of the address book. Note - the Flag bits are defined as: Description: Set the Lock bit for the specified MAC address. Parameter: Store the MAC address into DataReg5 DataReg0, with DataReg5 contains the MSB of the MAC address and DataReg0 contains the LSB. Result: the state machine will seek for an entry with matched MAC address, and set the Lock bit of the entry. The result is indicated by the Result register. Command 0BH Description: Set the Filter flag for the specified MAC address. Parameter: Store the MAC address into DataReg5 DataReg0, with DataReg5 contains the MSB of the MAC address and DataReg0 contains the LSB. Result: the state machine will seek for an entry with matched MAC address, and set the Filter bit of the entry. The result is indicated by the Result register. Command 0CH b7 b6 b5 b4 b3 Rsvd Rsvd Filter Lock New b2 Old b1 b0 Age Valid where: * * * * * Description: Delete the specified MAC address from the address table. Filter - 1 indicates the frame heading to this address should be dropped. Lock - 1 indicates the entry should never be changed or aged out. New - 1 indicates the entry is a newly learned address. Old - 1 indicates the address has been aged out. Age - 1 indicates the address has not 12 ACD Confidential. Do Not Reproduce. Use under Non-Disclosure Agreement only. Data Sheet: ACD80800 wait for the CPU to send the System Start command before the initialization process can be started. bit 5:3 - UARTID, shared with CPUD5:CPUD3, 3-bit ID for UART communication. Parameter: Store the MAC address into DataReg5 DataReg0, with DataReg5 contains the MSB of the MAC address and DataReg0 contains the LSB. * * Command 11H Description: Read next entry of address book. Parameter: None Result: The result is indicated by the Result register. If the command is completed with no error, the content of the address book entry pointed by Read Pointer will be stored into the Data registers. The MAC address will be stored into DataReg5 - DataReg0, with DataReg5 contains the MSB of the MAC address and DataReg0 contains the LSB. The port number is stored in DataReg6, and the Flag bits are stored in DataReg7. The Read Pointer will be increased by one. Command 20H Result: The result is indicated by the Result register. If the command is completed with no error, the content of first new entry of the address book will be stored into the Data registers. The MAC address will be stored into DataReg5 - DataReg0, with DataReg5 contains the MSB of the MAC address and DataReg0 contains the LSB. The port number is stored in DataReg6, and the Flag bits are stored in DataReg7. The Read Pointer is set to point to this entry. Command 31H Description: Read next new entry. Parameter: None Result: The result is indicated by the Result register. If the command is completed with no error, the content of next new entry from the Read Pointer of the address book will be stored into the Data registers. The MAC address will be stored into DataReg5 DataReg0, with DataReg5 contains the MSB of the MAC address and DataReg0 contains the LSB. The port number is stored in DataReg6, and the Flag bits are stored in DataReg7. The Read Pointer is set to point to this entry. Command 40H Description: Read first valid entry. Parameter: None Result: The result is indicated by the Result register. If the command is completed with no error, the content of first valid entry of the address book will be stored into the Data registers. The MAC address will be stored into DataReg5 - DataReg0, with DataReg5 contains the MSB of the MAC address and DataReg0 contains the LSB. The port number is stored in DataReg6, and the Flag bits are stored in DataReg7. The Read Pointer is set to point to this entry. Command 21H Description: Read first aged entry. Parameter: None Result: The result is indicated by the Result register. If the command is completed with no error, the content of first aged entry of the address book will be stored into the Data registers. The MAC address will be stored into DataReg5 - DataReg0, with DataReg5 contains the MSB of the MAC address and DataReg0 contains the LSB. The port number is stored in DataReg6, and the Flag bits are stored in DataReg7. The Read Pointer is set to point to this entry. Command 41H ACD Confidential. Do Not Reproduce. Use under Non-Disclosure Agreement only. Description: Read next valid entry. Parameter: None Result: The result is indicated by the Result register. If the command is completed with no error, the content of next valid entry from the Read Pointer of the address book will be stored into the Data registers. The MAC address will be stored into DataReg5 DataReg0, with DataReg5 contains the MSB of the MAC address and DataReg0 contains the LSB. The port number is stored in DataReg6, and the Flag bits are stored in DataReg7. The Read Pointer is set to point to this entry. Command 30H Description: Read next aged entry. Parameter: None Result: The result is indicated by the Result register. If the command is completed with no error, the content of next aged entry from the Read Pointer of the address book will be stored into the Data registers. The MAC address will be stored into DataReg5 DataReg0, with DataReg5 contains the MSB of the Description: Read first new page. 13 Data Sheet: ACD80800 been visited for current age cycle. Valid - 1 indicates the entry is a valid one. Rsvd - Reserved bits. Parameter: None Description: Read next valid entry. Parameter: None Command 50H 14 ACD Confidential. Do Not Reproduce. Use under Non-Disclosure Agreement only. Result: The result is indicated by the Result register. If the command is completed with no error, the content of next filtered entry from the Read Pointer of the Parameter: None address book will be stored into the Data registers. The MAC address will be stored into DataReg5 Result: The result is indicated by the Result register. If DataReg0, with DataReg5 contains the MSB of the the command is completed with no error, the content MAC address and DataReg0 contains the LSB. The of first locked entry of the address book will be stored port number is stored in DataReg6, and the Flag bits into the Data registers. The MAC address will be are stored in DataReg7. The Read Pointer is set to stored into DataReg5 - DataReg0, with DataReg5 point to this entry. contains the MSB of the MAC address and DataReg0 contains the LSB. The port number is stored in Command 80H DataReg6, and the Flag bits are stored in DataReg7. Description: Read first entry with specified port The Read Pointer is set to point to this entry. number. Command 51H Parameter: Store port number into DataReg6. Description: Read next locked entry. Result: The result is indicated by the Result register. If Parameter: None the command is completed with no error, the content of first entry of the address book with the said port Result: The result is indicated by the Result register. If number will be stored into the Data registers. The the command is completed with no error, the content MAC address will be stored into DataReg5 of next locked entry from the Read Pointer of the DataReg0, with DataReg5 contains the MSB of the address book will be stored into the Data registers. MAC address and DataReg0 contains the LSB. The The MAC address will be stored into DataReg5 port number is stored in DataReg6, and the Flag bits DataReg0, with DataReg5 contains the MSB of the are stored in DataReg7. The Read Pointer is set to MAC address and DataReg0 contains the LSB. The point to this entry. port number is stored in DataReg6, and the Flag bits are stored in DataReg7. The Read Pointer is set to Command 81H point to this entry. Description: Read next valid entry. Command 60H Parameter: Store port number into DataReg6. Description: Read first filtered page. Result: The result is indicated by the Result register. If Parameter: None the command is completed with no error, the content of next entry from the Read Pointer of the address Result: The result is indicated by the Result register. If book with the said port number will be stored into the the command is completed with no error, the content Data registers. The MAC address will be stored into of first filtered entry of the address book will be stored DataReg5 - DataReg0, with DataReg5 contains the into the Data registers. The MAC address will be MSB of the MAC address and DataReg0 contains the stored into DataReg5 - DataReg0, with DataReg5 LSB. The port number is stored in DataReg6, and the contains the MSB of the MAC address and DataReg0 Flag bits are stored in DataReg7. The Read Pointer is contains the LSB. The port number is stored in set to point to this entry. DataReg6, and the Flag bits are stored in DataReg7. The Read Pointer is set to point to this entry. Description: Read first locked entry. Data Sheet: ACD80800 MAC address and DataReg0 contains the LSB. The port number is stored in DataReg6, and the Flag bits are stored in DataReg7. The Read Pointer is set to point to this entry. Command 61H Figure-4: Format of a 48-bit MAC Address in a Data Register FRAME BITS b7 b0 b15 b8 b23 b16 b31 b24 b39 b32 b47 b40 b 7 b 6 b 5 b 4 b 3 b 2 b 1 b 0 D5 x x b 4 6 b 4 5 b 4 4 b 4 3 b 4 2 b 4 1 b 4 7 D4 b 3 9 b 3 8 b 3 7 b 3 6 b 3 5 b 3 4 b 3 3 b 3 2 D3 b 3 1 b 3 0 b 2 9 b 2 8 b 2 7 b 2 6 b 2 5 b 2 4 D2 b 2 3 b 2 2 b 2 1 b 2 0 b 1 9 b 1 8 b 1 7 b 1 6 D1 b 1 5 b 1 4 b 1 3 b 1 2 b 1 1 b 1 0 b 9 b 8 Command FFH Description: System reset. Parameter: None Result: This command will reset the ARL system. All entries of the address book will be cleared. Note: The handling of the MAC address is shown in figure 4. Special attention should be given to the location of bit 47 of the MAC address, which is at bit 0 of D5. The software needs to be aware of this and make the corresponding adjustment. 15 ACD Confidential. Do Not Reproduce. Use under Non-Disclosure Agreement only. D0 b 0 7 b 0 6 b 0 5 b 0 4 b 0 3 b 0 2 b 0 1 b 0 0 Data Sheet: ACD80800 Figure-5: Timing Of CPU Read Operation t1 CPUAx t2 t3 nOE t4 t6 nCS CPUDx HIGH-Z VALID DATA t7 t5 t8 t9 HIGH-Z Time t1 t2 t3 t4 t5 t6 t7 t8 t9 Description Read cycle time Address access time Output hold time nOE access time nCE access time nOE to Low-Z output nCE to Low-Z output nOE to High-Z output nCE to High-Z output Min 50 50 0 0 0 - Typ - Max 45 45 5 5 Unit ns ns ns ns ns ns ns ns ns 16 ACD Confidential. Do Not Reproduce. Use under Non-Disclosure Agreement only. Data Sheet: ACD80800 8. TIMING DESCRIPTIONS Figure-6: Timing Of CPU Write Operation t1 CPUAx t2 t4 nCE t3 t5 t6 nWE t7 CPUDx t8 ACD Confidential. Do Not Reproduce. Use under Non-Disclosure Agreement only. VALID DATA t9 Time Description Min Typ Max Unit t1 t2 t3 t4 t5 t6 t7 t8 Write Cycle Time Address Valid to Write End Address Hold for Write End nCE to Write End Address Setup time WE pulse width Data Valid to Write End Data Hold for Write End 30 30 0 25 0 25 30 0 - - ns ns ns ns ns ns ns ns 17 Data Sheet: ACD80800 Absolute Maximum Ratings Operation at absolute maximum ratings is not implied exposure to stresses outside those listed could cause permanent damage to the device. DC Supply voltage : VDD DC input current: Iin DC input voltage: Vin DC output voltage: Vout -0.3V ~ +4.5V +/-10 mA -0.3 ~ VDD + 0.3V -0.3 ~ VDD + 0.3V Recommended Operation Conditions Supply voltage: VDD Operating temperature: Ta Maximum Power dissipation 3.3V+/-10% 0 C -70 C 900mW o o 18 ACD Confidential. Do Not Reproduce. Use under Non-Disclosure Agreement only. Data Sheet: ACD80800 9. ELECTRICAL SPECIFICATION E1 E2 ZD PQFP-128 Symble A1 A2 D1 D2 e E1 E2 f g L1 L2 R1 R2 ZD Min 0.25 2.57 na na na na na 0.13 0.13 0.73 na 0.13 0.13 na Nom 0.33 2.71 23.2 18.5 0.5 17.2 12.5 0.15 0.2 0.88 1.6 na 0.3 0.75 Max na 2.87 na na na na na 0.17 0.28 1.03 na na na na D2 g A2 e D1 f R2 L1 L2 A 1 19 ACD Confidential. Do Not Reproduce. Use under Non-Disclosure Agreement only. A2 R1 Data Sheet: ACD80800 10. PACKAGING |
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